1. Field of the Invention
This invention relates in general to the field of fabricating semiconductor memory devices, and more particularly to a method for fabricating a storage plate of a capacitor suitable for a semiconductor memory device.
2. Description of Related Art
A capacitor is a widely used electrical component. In the present semiconductor integrated circuit industry, a capacitor plays an indispensable role in the field of semiconductor circuit design. The capacitor can be utilized in many kinds of electrical devices, such as dynamic random access memory (DRAM), oscillators, time-delay circuits, AD/DA converters, and other applications. Basically, a dielectric layer sandwiched between two conductive layers (i.e. storage plate) constitutes a capacitor. The capability of charge storage in a capacitor is determined by the following three physical parameters: (1) the thickness of the dielectric layer; (2) the surface area of the storage plate; and (3) the electrical or mechanical properties of the dielectric layer and the storage plate.
An example can be found in today's DRAM cell, which includes a transistor and a capacitor for storing data charge. In order to improve the integration density of a DRAM device, the size of each memory cell is continuously being shrunk. As known by those skilled in this art, the capacitor should have enough capacity to avoid data loss. Therefore, many attempts have been bade to maintain sufficient surface area of the storage plate in the capacitor, even the horizontal area of a memory cell is decreased.
Highly integrated DRAM requires three-dimensional capacitor structure such as that of a stack-type capacitor. For example, a "bristle-shaped" capacitor structure has been developed to form a capacitor with rugged storage plate surface above the transistor. This structure can achieve the advantages of low soft error rate and high capacitance if a suitable dielectric layer with high dielectric constant is used. The fabricating processes for three-dimensional capacitors, however, are more complicated than other conventional techniques. This results in increased manufacturing cost.
R.0.C. patent No. 239,234 discloses a method of fabricating a bristle-shaped storage plate of a semiconductor capacitor. The processing steps of this prior art are now described in detail, with reference to FIGS. 1 to 4. First, as shown in FIG. 1, a silicon wafer is subjected to a conventional process for forming a field oxide and a transistor consisting of gate, source and drain regions (not shown). To simplify the drawing, a substrate 20 with uniform surface is used to depict the above configuration.
Next, appropriate processing steps are performed to form a storage plate of a capacitor on the substrate 20. A silicon dioxide layer 23 is formed on the substrate 20 by chemical vapor deposition (CVD). The silicon dioxide layer 23 is then etched to form a contact window. A polysilicon layer 24 is formed on the silicon dioxide layer 23 by a CVD process and connected to one of the source and drain regions of the transistor through the contact window. Another silicon dioxide layer 31 and polysilicon layer 32 are successively deposited on the polysilicon layer 24.
An aluminum layer 33 is deposited on the surface of the polysilicon layer 32. The entire substrate is then annealed at a temperature between 400.degree. C. to 577.degree. C. The aluminum layer 33 and the polysilicon layer 32 are dissolved and reacted with each other. However, due to the insufficiency of solubility, aluminum precipitates with variant sizes remain on the polysilicon layer 32 and the silicon dioxide layer 31. Referring to FIG. 2, the non-reacted aluminum 33 is etched away by aqua regia solution (one part of nitric acid mixed with three parts of hydrochloric acid) until the silicon dioxide layer 31 is exposed. This results in forming a plurality of silicon nodules 320 of sizes between 500 .ANG. to 5000 .ANG..
Referring to FIG. 3, using the silicon nodules 320 as masks, the silicon dioxide layer 31 is etched by a reactive ion etching (RIE) process to form a plurality of oxide islands 310 with sizes of between 500 .ANG. to 5000 .ANG.. Then, another etching step is performed by using the oxide islands 310 as masks to remove the silicon nodules 320 as well as etch the polysilicon layer 24 to a predetermined depth, thereby forming a plurality of polysilicon pillars to provide a rugged surface. After that, as shown in FIG. 4, the oxide islands 310 is removed by dipping the substrate in hydrofluoric acid (HF) solution, completing the fabrication of a storage plate of a capacitor.
However, the above method is not effective in mass production since it needs complicated processing steps to form the bristle-shaped storage plate. In addition, the size of each silicon nodules can not be controlled accurately, because they are formed utilizing the insufficiency of solubility between aluminum and polysilicon.